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DICA LESSON PLAN
ANDHRA LOYOLA INSTITUTE OF ENGINEERING AND TECHNOLOGY
DEPARTEMENT OF ELECTRONICS AND
COMMUNICATION ENGINEERING
DIGITAL IC APPILICATIONS (DICA)
Teacher/Instructor: Mr.K.SRINIVASA RAO
Assistant Professor
Semester/Year: I/ III
Course
objectives:
1.
Introduction to logic
families and interfacing concepts for
digital design.
2.
Behavioral,Dataflow and Structural
modeling of digital circuits using VHDL.
3. This course aims to provide students
with the understanding of different Combinational and Sequential circuits with
the help of VHDL programs .
Course Outcomes:
1 |
Factual |
CO1:Students able to understand the structure of commercially available digital integrated circuit
families. |
2 |
Conceptual |
CO
2:
Students able to Learn the basics of IEEE Standard 1076 Hardware
Description Language (VHDL). CO
3: Students
able to write behavioural models of digital circuits in VHDL.
|
3 |
Procedural |
CO
4: Students
able to analyze and design basic digital circuits with
combinatorial logic circuits using VHDL.and IC’s. CO5: Students able to analyze and design basic digital circuits with sequential logic
circuits using VHDL.and IC’s… |
4 |
Applied |
CO
6:
Students able to understand the concepts
of FSM. |
Text
Books:
1.
Digital Design Principles & Practices – John F. Wakerly, PHI/ Pearson
Education Asia, 3rd Ed., 2005.
2.
VHDL Primer – J. Bhasker, Pearson Education/ PHI, 3rd Edition.
References:
1.
Fundamentals of Digital Logic with VHDL Design- Stephen Brown, ZvonkoVranesic,
McGrawHill, 3rdEdition.
Contents/Activities:
1 |
Factual |
1.NPTEL
Videos 2.Disscusion
Forum On Comparing Logic Families |
2 |
Conceptual |
1.Laborartry
Exercises 2.NPTEL
Videos 3.
Discussion Forum On Comparing The Different Modelling Styles In VHDL |
3 |
Procedural |
1.
NPTEL Videos 2.Disscusion
Forum On Modelling of Combinational and Sequential Circuits |
4 |
Applied |
1.
NPTEL Videos 2.
Discussion Forum On Current Trends In
Designing The Complex Digital Circuits 3.
Poll On Tools Used In Industry |
Schedule
and Sequence:
Session/week/
Module |
Topic |
Objectives |
Before Class -
Videos, e-Books, Case studies |
In-Class –
Activities, Quiz
|
Post Class -
Assignment, Discussion Forum |
UNIT-1: DIGITAL LOGIC FAMILIES AND INTERFACING |
|||||
1 |
Introduction
to Logic Families |
Aims
to learn various Logic Families. To
understand the operation of CMOS Inverter |
Video link: 1.https://www.youtube.com/watch?v=PM-4emVKbQg
|
1.Defining
the objective of course(10 min) 2.Types
of Logic
Families(20 min) 3.Operation
of CMOS Inverter(15 min) 4.Conclusion
of session(5 min) |
Discussion
Forum on Logic
Families
|
2 |
CMOS
Logic |
To
understand the design of CMOS 2-Input NAND and NOR gates |
1.Video links: ww.youtube.com/watch?v=8caQpnxa3iE
2.Video links:
https://www.youtube.com/watch?v=7OEkX1ScKBE |
Explanation
of
CMOS 2-Input NAND and NOR gates (50
min) |
Assignment: Function table for CMOS
2-Input NAND and NOR gates |
3 |
Design
of AND and OR gates using CMOS logic |
To
understand the design of CMOS 2-Input AND and OR gates |
Document link:
1.
|
Explanation of
CMOS 2-Input AND and OR gates (50
min) |
Assignment: Function table for CMOS
3-Input AND Gate |
4 |
Logic
diagram for AND-OR-INVERT and OR-AND-INVERT gates |
To
understand the design of AND-OR-INVERT gate circuits using CMOS |
Video link: https://www.youtube.com/watch?v=mCNeR4uUorQ
|
Logic
diagram for AND-OR-INVERT (25 min)
OR-AND-INVERT
gates –(25 min) |
Assignment: Function table for
AND-OR-INVERT and OR-AND-INVERT gates |
5 |
Electrical
behavior of CMOS Circuits |
To
understand the DC Noise Margin with respect to CMOS Logic Family |
Video link:
https://www.youtube.com/watch?v=7hC7g_0WPVk&list=PL3pGy4HtqwD1X9CXdgXMTVGjb7rYd-qr6&index=21
|
Electrical
properties of CMOS Circuits (50 min) |
Assignment: Definitions
of Electrical properties of CMOS Circuits.
|
6 |
CMOS
steady state electrical behavior |
To
understand steady state electrical behavior |
Video link: https://www.youtube.com/watch?v=6sM3LM0ho90
|
Noise
Margin of CMOS at Steady state condition (50 min)
|
Discussion
forum:
discussion on Fanout , Loading effects |
7 |
CMOS dynamic electrical behavior |
To
understand dynamic electrical behavior |
Video link: https://www.youtube.com/watch?v=6sM3LM0ho90
|
CMOS dynamic electrical behaviour Logic Levels (25 min ) Noise
margin (25 min)
|
Discussion
forum:
discussion on output Load specifications for CMOS |
8 |
CMOS logic families |
To
know the different types of CMOS Logic families |
Document: http://instrumentacion.qi.fcen.uba.ar/hbase/electronic/logfam.html#c3 |
Speed
and Power characteristics of CMOS families (50 min)
|
Assignment: Speed
and Power characteristics of CMOS families Table |
9 |
2-Input NAND gate using Transistor-Transistor
Logic (TTL) |
To
understand Transistor-Transistor Logic (TTL) |
Video link: https://www.youtube.com/watch?v=ne2WK5Vpg8k
|
Introduction
to TTL -(10 min) 2-Input NAND gate using Transistor-Transistor
Logic -(40 min) |
Assignment: Circuit
Diagram of 2-Input NAND gate using Transistor-Transistor Logic
(TTL) |
10 |
TTL families |
To
know the different types of TTL Logic families |
Document: http://instrumentacion.qi.fcen.uba.ar/hbase/electronic/logfam.html#c3 |
Characteristics
of gates in TTL families (50 min) |
Assignment: Characteristics
of gates in TTL families Table |
11 |
CMOS/TTL interfacing |
To
understand CMOS/TTL interfacing |
Video link:
https://www.youtube.com/watch?v=7B-XkFt7L8k
|
Output
and Input Levels for interfacing CMOS
and
TTL families (50 min) |
Assignment: Output
and Input Levels for interfacing CMOS and
TTL families |
12 |
Low voltage CMOS logic and interfacing |
To
understand Low voltage CMOS logic and interfacing |
Document: http://wakerly.org/DDPP/DDPP3_mkt/c03samp2.pdf |
Comparison
of Logic Levels (50 min) |
Assignment: 3.3V
LVTTL and LVCMOS logic |
13 |
Emitter coupled logic(ECL) |
To
understand Emitter coupled logic(ECL) |
Video link:
https://www.youtube.com/watch?v=MqidrO1TPvQ |
Emitter coupled logic(ECL) (50 min) |
Discussion
forum:
discussion on Comparison of CMOS,TTL,ECL Technologies |
14 |
Comparison of CMOS,TTL,ECL Technologies |
Comparison of CMOS,TTL,ECL Technologies with
respect to different parameters like noise margin |
Document:
https://technobyte.org/logic-families-ttl-cmos-ecl-bicmos-difference/ |
Comparison
Table (50 min) |
Assignment: quiz
on unit-1 |
UNIT-2: INTRODUCTION TO VHDL |
|||||
1 |
VHDL Design flow |
To
understand the VHDL Design flow |
Document:
https://ashwinjs.files.wordpress.com/2018/01/unit-3-q-a.pdf |
1.Overview
of VHDL(10 min) 2.
Design flow
(40 min)
|
Assignment: VHDL Design flow diagram |
2 |
Program structure, Levels of abstraction |
To
know the basic Program structure of
VHDL |
Video link: https://www.youtube.com/watch?v=BDq8-QDXmek
|
Overview
of VHDL Design Units (50 min) |
Discussion
forum:
discussion on Levels of abstraction
and Types of Modelling |
3 |
Elements of VHDL: Data types, data objects, |
To
know the basic data types required for VHDL Program |
1.Video
link: https://www.youtube.com/watch?v=k6eHc6kUJkk
2.Video
link: https://www.youtube.com/watch?v=9mRNPlbmjx8
|
Data
Types (35 min) data objects (15 min) |
Assignment: Write
the Data types of VHDL |
4 |
operators |
To
know the basic Operators of VHDL |
Video
link: https://www.youtube.com/watch?v=3LyEzOEmEIU&list=PLEdaowO6UzNENeQ2WHyGC6mlmggnnhMD6&index=3
|
Operators
of VHDL(50 min) |
Assignment: Operators
of VHDL |
5 |
Identifiers |
To know the basic Identifiers of VHDL |
Video
link: |
Identifiers of VHDL(50 min) |
Assignment: Identifiers of VHDL |
6 |
Packages |
To know the basic Packages of VHDL |
1.Video
link: https://www.youtube.com/watch?v=ue6ZCpWn0fM 2.Video
link: https://www.youtube.com/watch?v=mwJ3uMWvJX0 |
1.Package Declaration(15
min) 2. Packages Body (35 min) |
Assignment: Give
the syntax for Package |
7 |
Libraries and Bindings |
To know the basic Libraries and Bindings of VHDL |
Video
link: https://www.youtube.com/watch?v=ue6ZCpWn0fM |
1. basic Libraries (25 min) 2. Binding (25 min)
|
Discussion
forum:
discussion on basic Libraries
used in VHDL |
8 |
Subprograms |
To
understand the usage of Subprograms in
vhdl |
Video
link: https://www.youtube.com/watch?v=m9mA4ZdyAJM |
Syntax for Subprograms (50 min)
|
Assignment: Write
a VHDL program to explain Subprograms |
9 |
VHDL Programming using structural
modeling.
|
To know the structural
modelling of VHDL
|
Video
link: https://www.youtube.com/watch?v=t3b08P3ee2g
|
1.Syntax for structural
modelling (25 min) 2.Example(25 min)
|
Assignment: Write
a VHDL program for Half Adder using structural model |
10 |
VHDL Programming using data flow modeling.
|
To know the data flow
modelling of VHDL
|
Video
link: https://www.youtube.com/watch?v=w2woejCFWBA |
1.Syntax for data flow modelling (25 min) 2.Example(25 min)
|
Assignment: Write
a VHDL program for Half Adder using data flow
model |
11 |
VHDL program for 2x4 Decoder. |
To
know the VHDL programming |
Video
link: https://www.youtube.com/watch?v=iir1ahUmSGc
|
VHDL program for 2x4 Decoder (50 min)
|
Assignment: Write
a VHDL program for 2x4
Decoder using behavioural model |
UNIT-3: BEHAVIORAL MODELLING |
|||||
1 |
Process statement |
To understand and use of Process statement. |
Video
link: https://www.youtube.com/watch?v=VBUyqOyeueI
|
Syntax for Process statement (15 min) example(35 min) |
Assignment: Write
a behavioural model program for Half adder.
|
3 |
Variable assignment statement and Signal assignment statement |
To understand and use of Variable assignment statement and Signal assignment s statements. |
1.Video
link: https://www.youtube.com/watch?v=6PWiFdwJTzw 2.Video
link: https://www.ee.iitb.ac.in/~smdp/DKStutorials/vhdl-overview.pdf |
Declaration of Variable assignment statement (25 min) Signal assignment statement (25 min) |
Discussion
forum:
discussion on Signal assignment
statement
|
4 |
wait statement ,
|
To understand and use of wait statement. |
Video
link: https://www.youtube.com/watch?v=HzalKOi6ObM
|
Syntax for wait statement (50 min) |
Discussion
forum:
discussion on Signal wait statement
|
5 |
if statement, case statement |
To understand the types of delays in behavioural
modelling |
Video
link: https://www.youtube.com/watch?v=VBUyqOyeueI
|
Syntax for if statement (25 min)
Syntax for case statement (25min)
|
Assignment: Write
a behavioural model program for 2*1 Multiplexer using case statement
|
6 |
null statement, loop
statement |
To understand and use of null statement and loop
statements in behavioral modelling |
https://www.ee.iitb.ac.in/~smdp/DKStutorials/vhdl-overview.pdf
|
Syntax for null statement and loop
statements(30 min) example (20
min)
|
Discussion
forum:
discussion on loop statement
|
7 |
exit statement, next statement |
To understand and use of exit statement in behavioral modelling |
Document: https://www.ee.iitb.ac.in/~smdp/DKStutorials/vhdl-overview.pdf
|
Syntax for exit
statement and next statements (50 min) |
Discussion
forum:
discussion on exit statement |
8 |
assertion statement, more on signal assignment statement |
To understand the use of
different signal assignments in behavioral modelling |
Document: https://www.ee.iitb.ac.in/~smdp/DKStutorials/vhdl-overview.pdf
|
Syntax for assertion
statement and more on signal assignment statements (50 min) |
Discussion
forum:
discussion on signal assignment statement |
9 |
Inertial Delay Model |
To understand the Inertial Delay Model in behavioral modeling |
Document: https://www.iitg.ac.in/asahu/cs223-11/03-VHDL.pdf |
Syntax for Inertial
Delay Model (50 min) |
Assignment: Give
the example of Non inverting Buffer using Inertial Delay Model |
10 |
Transport Delay Model |
To understand the Transport Delay Model in behavioral modeling |
Document: https://www.iitg.ac.in/asahu/cs223-11/03-VHDL.pdf |
Syntax for Transport
Delay Model (50 min) |
Assignment: Give
the example of Non inverting Buffer using Transport Delay Model |
11 |
Creating Signal Waveforms, Signal Drivers |
To understand the Signal Drivers in behavioral modeling |
Video
link: https://www.youtube.com/watch?v=pZmU6GWPNtU
|
Signal Drivers (25 min) Effect of Inertial Delay on Signal Drivers ( 25 min) |
Assignment: Write
the effect of Inertial Delay and Transport Delay on Signal Drivers |
12 |
Other Sequential Statements |
To understand Return statement in behavioral modelling |
--- |
Procedure call statement ( 30 min) Return statement (20 min) |
--- |
13 |
Multiple Processes and Logic Synthesis |
To understand the Logic Synthesis |
Video
link: https://www.youtube.com/watch?v=EculfHy8ZTQ
|
Multiple Processes ( 30 min) Logic Synthesis ( 20 min) |
Assignment: Write
a VHDL program using Multiple Processes |
14 |
Inside a logic Synthesizer |
To understand the steps
of Logic Synthesis |
Video
link: https://www.youtube.com/watch?v=EculfHy8ZTQ
|
Inside a logic Synthesizer ( 50 min)
|
--- |
UNIT-4: COMBINATIONAL LOGIC DESIGN |
|||||
1 |
Binary Adder-Subtractor |
To understand the
principle of Binary Adder and
Subtractor |
1.Video
link: https://www.youtube.com/watch?v=KHgrJrcHr70
2.
Video link: https://www.youtube.com/watch?v=6OKQJCnx3is
3.
Video link: https://www.youtube.com/watch?v=MskwR5lBS7w |
1.Binary Adder(20min) 2.Half adder and Full adder(20 min) 3.Binary Subtractor (10min) |
Assignment: Design
and Write a VHDL program for Full adder using Half adder and its test bench |
2 |
Ripple Adder |
To understand the design
of Ripple Adder |
1.Video
link: https://www.youtube.com/watch?v=YBY0k5mIQy0
|
Design of Ripple
Adder (50 min) |
Assignment: Explain
the design the Ripple Adder with the
help of FF |
3 |
Look Ahead Carry Generator |
To understand the design
of Look Ahead Carry Generator |
Video
link: |
Design of Look
Ahead Carry Generator (50 min) |
Assignment: Explain
the design the Look Ahead Carry
Generator |
4 |
ALU |
To understand the design
of ALU |
1.Video
link: https://www.youtube.com/watch?v=RkAE4zE4uSE 2.Video
link: https://www.youtube.com/watch?v=kpzx5U0CKqs
|
Design of ALU
(50 min) |
Assignment: Design
and Write a VHDL program for 4-bit ALU |
5 |
Decoders |
To understand the design
of Decoders |
Video
link: |
Design of Decoders (50 min) |
Assignment: Design
and Write a VHDL program for 2 to
4 Decoder |
6 |
Encoders |
To understand the design
of Encoders |
Video
link: |
Design of Encoders (50 min) |
Assignment: Design
and Write a VHDL program for 4 to 2
Decoder. |
7 |
Multiplexers and demultiplexers |
To understand the design
of Multiplexers and demultiplexers |
1.Video
link: https://www.youtube.com/watch?v=7G1i5PUgz3w
2.Video
link: |
1. Design of
Multiplexers (25 min) 2. Design of
demultiplexers (25 min) |
Assignment: Design
and Write a VHDL program for 4x1 Multiplexer |
8 |
Parity circuits |
To understand the concept
of Parity and encoder with parity |
Video
link: |
Parity circuit Diagrams(50 min) |
Discussion
forum:
discussion on Parity circuits |
9 |
Comparators |
To understand the
principle of Comparators |
Video
link: |
Principle of
Comparators (50 min) |
Assignment: Design
and Write a VHDL program for 2-bit Comparator |
10 |
Barrel Shifter |
To understand the
principle of Barrel Shifter |
Video
link: |
Design of
Barrel Shifter (50 min) |
Assignment: Design of Barrel
Shifter |
11 |
Simple Floating-Point Encoder |
To understand the
principle of Simple Floating-Point Encoder |
Document: |
Design of
Simple Floating-Point Encoder (50 min) |
Assignment: Design of Simple
Floating-Point Encoder with Logic Diagram |
12 |
Dual Priority Encoder |
To understand the
principle of Dual Priority Encoder |
Document: |
Design of
Dual Priority Encoder (50 min) |
Assignment: Design of Dual
Priority Encoder with Logic Diagram |
13 |
Design considerations of the above combinational
logic circuits with relevant Digital ICs, modeling of above ICs using VHDL |
To know different combinational logic circuits with relevant
Digital ICs and Programming |
1.
Document: https://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm
2.
Document: https://www.eng.auburn.edu/~nelsovp/courses/elec4200/Slides/VHDL%202%20Combinational.pdf
|
combinational logic circuits with relevant
Digital ICs and modeling of above ICs using VHDL (50 min) |
Quiz: quiz
on unit-4
|
UNIT-5: SEQUENTIAL LOGIC DESIGN |
|||||
1 |
SSI Latches |
To
learn the function of Latches |
Video
link: |
Function of Latches and
Difference between Latches and FF.( 50 min) |
Discussion
forum:
discussion on Difference between Latches
and FF |
2 |
Flip Flops |
To
learn the function of FFs and to learn Types of FF |
Video
link: |
Function of FF(10 min) Types of FF – D,JK,SR.( 40 min) |
Assignment: Design
and Write a VHDL program for JK FF. |
3 |
Ring Counter
|
To understand the design
and principle of Ring
Counter
|
Video
link: |
Design of Ring Counter using FF ( 50 min) |
Assignment: Explain the design of Ring Counter using FF
|
4 |
Johnson Counter |
To understand the design
and principle of Johnson
Counter
|
Video
link: |
Design of Johnson Counter using FF ( 50 min) |
Assignment: Explain the design of Johnson Counter using FF
|
5 |
Design of Modulus N-Synchronous Counters |
To understand the design
and principle of Modulus
N-Synchronous Counters |
Video
link: https://www.youtube.com/watch?v=Gc3DL-tmr-g
|
Design of Modulus N-Synchronous Counters using FF ( 50 min) |
Assignment: Explain the design of Modulus N-Synchronous Counters using FF
|
6 |
Shift Registers |
To understand the principle of Shift
Registers |
Video
link: https://www.youtube.com/watch?v=Iecj9xmIfXM&list=PL803563859BF7ED8C&index=21
|
Types of Shift Registers and their operation(50 min) |
Assignment: Explain the design of Shift Registers
|
7 |
Universal Shift Registers
|
To understand the principle of Universal
Shift Registers
|
Video
link: |
Types of Shift Registers and their operation(50 min) |
Assignment: Explain the design of Universal Shift Registers
|
8 |
Design considerations of the above sequential
logic circuits with relevant Digital ICs |
To know various sequential logic circuits with relevant Digital
ICs |
Document: |
sequential logic circuits with relevant Digital
ICs (50 min) |
Discussion
forum:
discussion on sequential logic
circuits with relevant Digital ICs |
9 |
Modeling of above ICs using VHDL |
To know the modelling of sequential logic using vhdl |
1.Document: http://wakerly.org/DDPP/DDPP3_mkt/c07samp4.pdf
|
Vhdl programming for
sequential circuits (50 min) |
Quiz: quiz
on unit-5
|
UNIT-6: SYNCHRONOUS
AND ASYNCHRONOUS SEQUENTIAL CIRCUITS |
|||||
1 |
State diagram |
To understand the states
and state diagram of FSM |
1.Video
link:
2.Video
link: https://www.youtube.com/watch?v=byFwNSeAjtM
|
1. Representation
of states ( 20 min) 2.how to draw state
diagram(30 min) |
Discussion
forum:
discussion on how to draw State
diagram for FSM |
2 |
state table, state assignment |
To understand the state table and state assignment of FSM |
Video
link: https://www.youtube.com/watch?v=-ETrFSbWOYQ |
1. how to prepare the state table from state diagram (20 min) 2. state assignment (30 min)
|
Discussion
forum:
discussion on state table and state
assignment |
3 |
choice of flip flops and derivation of next state
and output expressions |
To know the choice of flip flops and derivation of next state
and output expressions |
1.Video
link: https://www.youtube.com/watch?v=-7j9F5UKeCQ
2.Document: http://www.ece.tamu.edu/~xizhang/ECEN248/Chapter_7_8_Chapter_Part-I_Xi_Zhang.pdf |
choice of flip flops and derivation of next state
and output expressions (50 min) |
Discussion
forum:
discussion on choice of flip flops
for State Machines |
4 |
timing diagram |
To understand how to draw timing diagram for sequential circuits |
Document: https://courses.cs.washington.edu/courses/cse370/08wi/pdfs/lectures/14-Flip-flops.pdf |
timing
diagram for sequential circuits with examples(50 min) |
Discussion
forum:
discussion on how to draw timing diagram for sequential circuits |
5 |
State assignment problem: One hot encoding |
To understand and design One hot encoding |
1.Document: http://www.ece.tamu.edu/~xizhang/ECEN248/Chapter_7_8_Chapter_Part-I_Xi_Zhang.pdf
2.Document:
|
Design of One hot encoding (50
min) |
Assignment: Explain the design of One hot encoding. |
6 |
Mealy and Moore type FSM for serial adder |
To learn the Mealy and Moore type FSM |
1.Video
link: https://www.youtube.com/watch?v=O3If0Nr9to0
2.Video
link: |
1. Mealy and Moore type FSM (30 min) 2.Design the serial adder circuit using Mealy and Moore
Machine ( 20 min) |
Assignment: Explain the design of Mealy and Moore type FSM for serial adder. |
7 |
VHDL code for the serial adder |
To learn the design of serial adder and write VHDL code for the serial adder |
1.Video
link: https://www.youtube.com/watch?v=l_XqQyCxiQs
2.Document: |
Design of serial adder and write VHDL code for the serial
adder(50 min) |
Assignment:
Write VHDL code for the serial adder |
8 |
Analysis of Asynchronous circuits |
To learn the principal of Asynchronous circuits |
Video
link: |
1.Difference between Synchronous circuits and Asynchronous circuits(20 min) 2. Types of
Asynchronous circuits(30 min) |
Assignment:
Write various types of Asynchronous circuits |
9 |
State Reduction, State Assignment |
To understand the State Reduction and State Assignment Techniques |
Video
link:
|
1. State Reduction concept(20 min) 2. State
Assignment (30 min) |
Discussion
forum:
discussion on State Assignment for
Mealy and Moore type FSM |
10 |
A complete design example: The vending machine
controller |
To know the design of vending machine controller |
Video
link: |
the design of vending machine controller(50 min) |
Assignment:
Write the design of vending
machine controller |
Assessment:
Summative:
5
Formative:
25 (internal) +70(external) =95
SIGNATURE
OF THE FACULTY
SIGNATURE OF HEAD OF THE DEPARTMENT
Evaluation:
Formative Assessment – 50%
Summative Assessment – 50%
EDC UNIT-5 Material
EDC UNIT-5 Material
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EDC UNIT-5 Material
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EDC UNIT-2 Material
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EDC UNIT-4 Material